\doxysection{EXTI\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_e_x_t_i___type_def}{}\label{struct_e_x_t_i___type_def}\index{EXTI\_TypeDef@{EXTI\_TypeDef}}


External Interrupt/\+Event Controller.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_af99061804746af139249d9d85b513cbb}{RTSR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a3f716a769d6f26f1c31197671829026c}{FTSR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_af56898c09c0706ab0b5c19348396f5dd}{SWIER1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a29fcf9c1c8f603e5df9be8aaedacf09a}{D3\+PMR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_ae26f33abdf23c782e78cf7db562dd30e}{D3\+PCR1L}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a3d4bf0cc0381bf71101673cca2896c54}{D3\+PCR1H}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a8f196bdc0e8832cdc52f3a5af1afe229}{RESERVED1}} \mbox{[}2\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a9670b69baeb2f676b54403a6fd7482dc}{RTSR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a518a0f964908240ac335bf137c2097f3}{FTSR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_ac537696dafad0997c5ebc4f4d21abd16}{SWIER2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_ae8ba258acaf3fcdc3649d9e1078a20c4}{D3\+PMR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_aad963c39c380c9aa9d204c02462aa250}{D3\+PCR2L}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_aac34328d21a4e01f7ce242529ba532a4}{D3\+PCR2H}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a8ed6bcee680685b8477673297c29928a}{RESERVED2}} \mbox{[}2\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a1181e87c3860c6c7553e0a4e5a2f8cf5}{RTSR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_ab2a64f72cfd9c9afee4f4e493052dc8e}{FTSR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a46ae82f4486d865d15cd405c1c32a171}{SWIER3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_aef538b88a58adc58ab80421865eea956}{D3\+PMR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_ab1d9dbc7a8c28c8b43c16354b0ff3430}{D3\+PCR3L}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_afb2c4a25d43a54dd07457588a4164f59}{D3\+PCR3H}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_acbfe5d52a83db98a3f6a60e0ef072615}{RESERVED3}} \mbox{[}10\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a6cf1565b24de1454ab65ed4fe87ca5aa}{IMR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a44c50101751493e6620e2bc91d98d183}{EMR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a4f3ada5d312a15ad5faa8d47f7834b50}{PR1}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a1ec7f1f8f8a67a891e261b1ed0d2e657}{RESERVED4}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a0d6bf1df9ad8ca71ac21d19a1a9c9375}{IMR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a36eec4d67b3fb7a34fe555be763e2347}{EMR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a70a4f12449826cb6aeceed7ee6253752}{PR2}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a9b21d9f2204938ece5c9ee8c22dca9e1}{RESERVED5}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a6e129c6e5d400434130e3a96eae09f45}{IMR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_a590056773009a97f5ea65db9587fe938}{EMR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_e_x_t_i___type_def_aacbc1583876d7be6a2e241ddf434d15c}{PR3}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
External Interrupt/\+Event Controller. 

\label{doc-variable-members}
\Hypertarget{struct_e_x_t_i___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_e_x_t_i___type_def_a3d4bf0cc0381bf71101673cca2896c54}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!D3PCR1H@{D3PCR1H}}
\index{D3PCR1H@{D3PCR1H}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3PCR1H}{D3PCR1H}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a3d4bf0cc0381bf71101673cca2896c54} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+D3\+PCR1H}

EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset\+: 0x14 \Hypertarget{struct_e_x_t_i___type_def_ae26f33abdf23c782e78cf7db562dd30e}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!D3PCR1L@{D3PCR1L}}
\index{D3PCR1L@{D3PCR1L}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3PCR1L}{D3PCR1L}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_ae26f33abdf23c782e78cf7db562dd30e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+D3\+PCR1L}

EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset\+: 0x10 \Hypertarget{struct_e_x_t_i___type_def_aac34328d21a4e01f7ce242529ba532a4}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!D3PCR2H@{D3PCR2H}}
\index{D3PCR2H@{D3PCR2H}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3PCR2H}{D3PCR2H}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_aac34328d21a4e01f7ce242529ba532a4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+D3\+PCR2H}

EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset\+: 0x34 \Hypertarget{struct_e_x_t_i___type_def_aad963c39c380c9aa9d204c02462aa250}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!D3PCR2L@{D3PCR2L}}
\index{D3PCR2L@{D3PCR2L}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3PCR2L}{D3PCR2L}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_aad963c39c380c9aa9d204c02462aa250} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+D3\+PCR2L}

EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset\+: 0x30 \Hypertarget{struct_e_x_t_i___type_def_afb2c4a25d43a54dd07457588a4164f59}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!D3PCR3H@{D3PCR3H}}
\index{D3PCR3H@{D3PCR3H}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3PCR3H}{D3PCR3H}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_afb2c4a25d43a54dd07457588a4164f59} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+D3\+PCR3H}

EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset\+: 0x54 \Hypertarget{struct_e_x_t_i___type_def_ab1d9dbc7a8c28c8b43c16354b0ff3430}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!D3PCR3L@{D3PCR3L}}
\index{D3PCR3L@{D3PCR3L}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3PCR3L}{D3PCR3L}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_ab1d9dbc7a8c28c8b43c16354b0ff3430} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+D3\+PCR3L}

EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset\+: 0x50 \Hypertarget{struct_e_x_t_i___type_def_a29fcf9c1c8f603e5df9be8aaedacf09a}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!D3PMR1@{D3PMR1}}
\index{D3PMR1@{D3PMR1}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3PMR1}{D3PMR1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a29fcf9c1c8f603e5df9be8aaedacf09a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+D3\+PMR1}

EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset\+: 0x0C \Hypertarget{struct_e_x_t_i___type_def_ae8ba258acaf3fcdc3649d9e1078a20c4}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!D3PMR2@{D3PMR2}}
\index{D3PMR2@{D3PMR2}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3PMR2}{D3PMR2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_ae8ba258acaf3fcdc3649d9e1078a20c4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+D3\+PMR2}

EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset\+: 0x2C \Hypertarget{struct_e_x_t_i___type_def_aef538b88a58adc58ab80421865eea956}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!D3PMR3@{D3PMR3}}
\index{D3PMR3@{D3PMR3}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3PMR3}{D3PMR3}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_aef538b88a58adc58ab80421865eea956} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+D3\+PMR3}

EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset\+: 0x4C \Hypertarget{struct_e_x_t_i___type_def_a44c50101751493e6620e2bc91d98d183}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!EMR1@{EMR1}}
\index{EMR1@{EMR1}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{EMR1}{EMR1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a44c50101751493e6620e2bc91d98d183} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+EMR1}

EXTI Event mask register, Address offset\+: 0x84 \Hypertarget{struct_e_x_t_i___type_def_a36eec4d67b3fb7a34fe555be763e2347}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!EMR2@{EMR2}}
\index{EMR2@{EMR2}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{EMR2}{EMR2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a36eec4d67b3fb7a34fe555be763e2347} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+EMR2}

EXTI Event mask register, Address offset\+: 0x94 \Hypertarget{struct_e_x_t_i___type_def_a590056773009a97f5ea65db9587fe938}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!EMR3@{EMR3}}
\index{EMR3@{EMR3}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{EMR3}{EMR3}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a590056773009a97f5ea65db9587fe938} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+EMR3}

EXTI Event mask register, Address offset\+: 0x\+A4 \Hypertarget{struct_e_x_t_i___type_def_a3f716a769d6f26f1c31197671829026c}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!FTSR1@{FTSR1}}
\index{FTSR1@{FTSR1}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FTSR1}{FTSR1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a3f716a769d6f26f1c31197671829026c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+FTSR1}

EXTI Falling trigger selection register, Address offset\+: 0x04 \Hypertarget{struct_e_x_t_i___type_def_a518a0f964908240ac335bf137c2097f3}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!FTSR2@{FTSR2}}
\index{FTSR2@{FTSR2}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FTSR2}{FTSR2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a518a0f964908240ac335bf137c2097f3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+FTSR2}

EXTI Falling trigger selection register, Address offset\+: 0x24 \Hypertarget{struct_e_x_t_i___type_def_ab2a64f72cfd9c9afee4f4e493052dc8e}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!FTSR3@{FTSR3}}
\index{FTSR3@{FTSR3}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FTSR3}{FTSR3}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_ab2a64f72cfd9c9afee4f4e493052dc8e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+FTSR3}

EXTI Falling trigger selection register, Address offset\+: 0x44 \Hypertarget{struct_e_x_t_i___type_def_a6cf1565b24de1454ab65ed4fe87ca5aa}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!IMR1@{IMR1}}
\index{IMR1@{IMR1}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IMR1}{IMR1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a6cf1565b24de1454ab65ed4fe87ca5aa} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+IMR1}

EXTI Interrupt mask register, Address offset\+: 0x80 \Hypertarget{struct_e_x_t_i___type_def_a0d6bf1df9ad8ca71ac21d19a1a9c9375}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!IMR2@{IMR2}}
\index{IMR2@{IMR2}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IMR2}{IMR2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a0d6bf1df9ad8ca71ac21d19a1a9c9375} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+IMR2}

EXTI Interrupt mask register, Address offset\+: 0x90 \Hypertarget{struct_e_x_t_i___type_def_a6e129c6e5d400434130e3a96eae09f45}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!IMR3@{IMR3}}
\index{IMR3@{IMR3}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IMR3}{IMR3}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a6e129c6e5d400434130e3a96eae09f45} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+IMR3}

EXTI Interrupt mask register, Address offset\+: 0x\+A0 \Hypertarget{struct_e_x_t_i___type_def_a4f3ada5d312a15ad5faa8d47f7834b50}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!PR1@{PR1}}
\index{PR1@{PR1}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PR1}{PR1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a4f3ada5d312a15ad5faa8d47f7834b50} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+PR1}

EXTI Pending register, Address offset\+: 0x88 \Hypertarget{struct_e_x_t_i___type_def_a70a4f12449826cb6aeceed7ee6253752}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!PR2@{PR2}}
\index{PR2@{PR2}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PR2}{PR2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a70a4f12449826cb6aeceed7ee6253752} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+PR2}

EXTI Pending register, Address offset\+: 0x98 \Hypertarget{struct_e_x_t_i___type_def_aacbc1583876d7be6a2e241ddf434d15c}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!PR3@{PR3}}
\index{PR3@{PR3}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PR3}{PR3}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_aacbc1583876d7be6a2e241ddf434d15c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+PR3}

EXTI Pending register, Address offset\+: 0x\+A8 \Hypertarget{struct_e_x_t_i___type_def_a8f196bdc0e8832cdc52f3a5af1afe229}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a8f196bdc0e8832cdc52f3a5af1afe229} 
uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+RESERVED1\mbox{[}2\mbox{]}}

Reserved, 0x18 to 0x1C \Hypertarget{struct_e_x_t_i___type_def_a8ed6bcee680685b8477673297c29928a}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!RESERVED2@{RESERVED2}}
\index{RESERVED2@{RESERVED2}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED2}{RESERVED2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a8ed6bcee680685b8477673297c29928a} 
uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+RESERVED2\mbox{[}2\mbox{]}}

Reserved, 0x38 to 0x3C \Hypertarget{struct_e_x_t_i___type_def_acbfe5d52a83db98a3f6a60e0ef072615}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!RESERVED3@{RESERVED3}}
\index{RESERVED3@{RESERVED3}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED3}{RESERVED3}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_acbfe5d52a83db98a3f6a60e0ef072615} 
uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+RESERVED3\mbox{[}10\mbox{]}}

Reserved, 0x58 to 0x7C \Hypertarget{struct_e_x_t_i___type_def_a1ec7f1f8f8a67a891e261b1ed0d2e657}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!RESERVED4@{RESERVED4}}
\index{RESERVED4@{RESERVED4}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED4}{RESERVED4}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a1ec7f1f8f8a67a891e261b1ed0d2e657} 
uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+RESERVED4}

Reserved, 0x8C \Hypertarget{struct_e_x_t_i___type_def_a9b21d9f2204938ece5c9ee8c22dca9e1}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!RESERVED5@{RESERVED5}}
\index{RESERVED5@{RESERVED5}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED5}{RESERVED5}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a9b21d9f2204938ece5c9ee8c22dca9e1} 
uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+RESERVED5}

Reserved, 0x9C \Hypertarget{struct_e_x_t_i___type_def_af99061804746af139249d9d85b513cbb}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!RTSR1@{RTSR1}}
\index{RTSR1@{RTSR1}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RTSR1}{RTSR1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_af99061804746af139249d9d85b513cbb} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+RTSR1}

EXTI Rising trigger selection register, Address offset\+: 0x00 \Hypertarget{struct_e_x_t_i___type_def_a9670b69baeb2f676b54403a6fd7482dc}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!RTSR2@{RTSR2}}
\index{RTSR2@{RTSR2}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RTSR2}{RTSR2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a9670b69baeb2f676b54403a6fd7482dc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+RTSR2}

EXTI Rising trigger selection register, Address offset\+: 0x20 \Hypertarget{struct_e_x_t_i___type_def_a1181e87c3860c6c7553e0a4e5a2f8cf5}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!RTSR3@{RTSR3}}
\index{RTSR3@{RTSR3}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RTSR3}{RTSR3}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a1181e87c3860c6c7553e0a4e5a2f8cf5} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+RTSR3}

EXTI Rising trigger selection register, Address offset\+: 0x40 \Hypertarget{struct_e_x_t_i___type_def_af56898c09c0706ab0b5c19348396f5dd}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!SWIER1@{SWIER1}}
\index{SWIER1@{SWIER1}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SWIER1}{SWIER1}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_af56898c09c0706ab0b5c19348396f5dd} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+SWIER1}

EXTI Software interrupt event register, Address offset\+: 0x08 \Hypertarget{struct_e_x_t_i___type_def_ac537696dafad0997c5ebc4f4d21abd16}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!SWIER2@{SWIER2}}
\index{SWIER2@{SWIER2}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SWIER2}{SWIER2}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_ac537696dafad0997c5ebc4f4d21abd16} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+SWIER2}

EXTI Software interrupt event register, Address offset\+: 0x28 \Hypertarget{struct_e_x_t_i___type_def_a46ae82f4486d865d15cd405c1c32a171}\index{EXTI\_TypeDef@{EXTI\_TypeDef}!SWIER3@{SWIER3}}
\index{SWIER3@{SWIER3}!EXTI\_TypeDef@{EXTI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SWIER3}{SWIER3}}
{\footnotesize\ttfamily \label{struct_e_x_t_i___type_def_a46ae82f4486d865d15cd405c1c32a171} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t EXTI\+\_\+\+Type\+Def\+::\+SWIER3}

EXTI Software interrupt event register, Address offset\+: 0x48 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
